1. Field of the Invention
The present invention relates to a solid-state imaging device from which data is read out on a column-parallel basis, a method of driving the device, and a camera system having the device.
2. Description of the Related Art
A CMOS image sensor can be manufactured using manufacturing processes similar to those used for common CMOS integrated circuits. A CMOS image sensor can be driven by a single power source and can be consolidated with analog circuits and logic circuits manufactured using CMOS processes into a single chip.
Thus, CMOS image sensors have a multiplicity of significant advantages including the fact that they can be implemented in combination with a small number of peripheral ICs.
It is the main trend in the related art to use one-channel (ch) output type CCD output circuits utilizing an FD amplifier having a floating diffusion (FD) layer.
On the contrary, CMOS image sensors include an FD amplifier provided at each pixel, and the main stream of this category is column-parallel output type products in which a certain row of a pixel array is selected and pixels in the row are simultaneously read in the direction of columns.
The reason for adopting such a configuration is as follows. It is difficult to obtain a sufficient driving capability from FD amplifiers provided in pixels alone. Therefore, a need for a reduced data rate arises, and parallel processing is considered advantageous at a low data rate.
A variety of proposals have been made on circuits to be used for reading out (outputting) pixel signals from column-parallel output type CMOS image sensors.
One of the most advanced types of such circuits is the type in which an analog-digital converter (hereinafter abbreviated as “ADC”) is provided for each column to obtain pixel signals from the column as digital signals.
For example, CMOS image sensors having such column-parallel type ADCs incorporated therein are disclosed in W. Yang et. al., “An Integrated 800×600 CMOS Image System”, ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 (Non-Patent Document 1) and JP-A-2005-278135 (Patent Document 1).
FIG. 1 is a block diagram showing an exemplary configuration of a solid-state imaging device (CMOS image sensor) 1 having column-parallel type ADCs incorporated therein.
As shown in FIG. 1, the solid-state imaging device 1 includes a pixel section 2, a vertical scan circuit (scan circuit) 3, a horizontal transfer scan circuit (column scan circuit) 4, a load circuit 5, and column-parallel processing section 6 formed by a group of ADCs.
Further, the solid-state imaging device 1 includes a digital-analog converter (hereinafter abbreviated as “DAC”) 7, an internal voltage generating circuit 8, and a timing control circuit 9.
The pixel section 2 is formed by disposing unit pixels 21 in the form of a matrix, each unit pixel including a photodiode (photoelectric conversion device) and an in-pixel amplifier.
In the pixel section 2, unit pixels 21 arranged in the same row are connected to the same row control line CTL, and unit pixels 21 arranged in the same column are connected to vertical signal lines 10-1 to 10-n for reading out signals.
The load circuit 5 includes load MOS transistors 51-1 to 51-n which are provided in association with columns of pixel alignment and which are connected to the vertical signal lines 10-1 to 10-n, respectively at the drains thereof and connected to a reference potential VSS at the sources thereof.
The gates of the load MOS transistors 51-1 to 51-n are connected to a supply line of a bias voltage VBIAS1 generated by the internal voltage generating circuit 8.
The load MOS transistors 51-1 to 51-n serve as current sources of source followers when pixels are read out.
The column-parallel processing section 6 includes a plurality of column processing circuits 61 each of which constitutes an ADC associated with a column of pixels.
Each of the column processing circuits (ADC) 61 includes a comparator 61-1 which compares a reference signal RAMP (Vslop) and an analog signal Vsl obtained from the respective pixel on each row line through the vertical signal line where the reference signal RAMP is a ramp waveform obtained by varying a reference signal generated by the DAC 7 stepwise.
Further, each of the column processing circuit 61 includes a counter 61-2 counting the time of the comparison carried out by the comparator 61-1 and a memory (latch) 61-3 holding the result of the counting carried out by the counter 61-2. The column processing circuit 61 also includes a transfer switch 61-4.
A bias voltage VBIAS3 input through an external bias input terminal T1 is supplied to the gate of a transistor serving as a current source of differential pair transistors of the comparator 61-1.
The column processing circuits 61 have an n-bit digital signal converting function, and one circuit 61 is disposed on each of the vertical signal lines (column lines) 10-1 to 10-n to form a column-parallel ADC block.
The output of each memory 61-3 is connected to the horizontal transfer line 11 which has a width of, for example, k bits.
K amplifier circuits (not shown) are provided in association with the horizontal transfer line 11.
A bias voltage VBIAS2 generated by the internal voltage generating circuit 8 is supplied to the DAC 7. The DAC 7 generates the reference signal RAMP (Vslop) which is a ramp waveform obtained by varying a reference signal stepwise and supplies the signal to the comparator 61-1 of each column processing circuit 61.
The timing control circuit 9 controls the timing of processes performed by the vertical scan circuit 3, the horizontal transfer scan circuit 4, the column-parallel processing section 6, and the DAC 7.
FIG. 2 is a timing chart of the circuits shown in FIG. 1.
At each column processing circuit (ADC) 61, an analog signal (potential Vsl) read out to the vertical signal line 10 is compared with the stepwise-varying reference signal RAMP (Vslop) at the comparator 61-1 disposed in the column.
At this time, the counter 61-2 keeps on counting until the levels of the analog potential Vsl and the reference signal RAMP (Vslop) cross each other to invert the output of the comparator 61-1, and the potential (analog signal) Vsl on the vertical signal line 10 is converted into a digital signal (A/D conversion takes place).
The A/D conversion takes place twice at each readout cycle.
The first A/D conversion takes place when a reset level (P-phase) of the unit pixels 21 is read out to the vertical signal lines 10 (10-1 to 10-n).
The reset level (P-phase) of each pixel has some variation.
The second A/D conversion takes place when signals obtained by photoelectric conversion performed at the unit pixels 21 are read out to the vertical signal lines 10 (10-1 to 10-n) (D-phase).
Since the D-phase level of each pixel also has some variation, levels in the P-phase are subtracted from levels in the D-phase, whereby correlated double sampling (CDS) is carried out.
Digital signals obtained by the conversion described above are recorded in the memories 61-3 and sequentially read out by the horizontal (column) transfer scan circuit 4 into an amplifier circuit through the horizontal transfer line 11, and the signals are finally output from the amplifier circuit.
A column-parallel output process is carried out as thus described.
The counting process of the counters 61-2 in the P-phase is referred to as “first-order sampling”, and the counting process of the counters 61-2 in the D-phase is referred to as “second-order sampling”.